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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:50:32 01/20/2010 
-- Design Name: 
-- Module Name:    SimpleProcessor - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- General package
use work.GeneralProperties.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SimpleProcessor is
    Port ( RESET        : in  STD_LOGIC;
           CLK          : in  STD_LOGIC;
           External     : inout  STD_LOGIC_VECTOR   ((bus_size-1) downto 0);
           MEM_WriteAdd : out  STD_LOGIC_VECTOR ((bus_size-1) downto 0);
           MEM_ReadAdd  : out  STD_LOGIC_VECTOR  ((bus_size-1) downto 0);
           MEM_Read     : out  STD_LOGIC;
           MEM_Write    : out  STD_LOGIC;			  
			  RUN          : out  STD_LOGIC;			  
			  MEM_Data_out : out  STD_LOGIC_VECTOR ((bus_size-1) downto 0);
           MEM_Data     : in  STD_LOGIC_VECTOR ((bus_size-1) downto 0));
end SimpleProcessor;

architecture Behavioral of SimpleProcessor is
  
  component ControlUnit is
    Port ( memory_data          : in     STD_LOGIC_VECTOR ((bus_size-1) downto 0);
	        memory_data_out      : out     STD_LOGIC_VECTOR ((bus_size-1) downto 0);
           memory_read_address  : out    STD_LOGIC_VECTOR ((bus_size-1) downto 0);			  
           memory_write_address : out    STD_LOGIC_VECTOR ((bus_size-1) downto 0);
			  memory_read          : out    STD_LOGIC;
			  memory_write         : out    STD_LOGIC;			  
           CLOCK                : in     STD_LOGIC;
           RESET                : in     STD_LOGIC;
			  InImediate           : out    STD_LOGIC_VECTOR ((bus_size - 6) downto 0);
			  Flags                : in     STD_LOGIC_VECTOR (3 downto 0);
			  RegisterAValue       : in     STD_LOGIC_VECTOR ((bus_size - 1) downto 0);
			  RegisterBValue       : in     STD_LOGIC_VECTOR ((bus_size - 1) downto 0);
			  SelMuxInput          : out    MultiplexSignals;
           SelAluOp             : out    ALU_operations;
			  SelShifterOp         : out    Shifter_operations;
			  RegFileWriteAddress  : out    ProcessorRegisters;
			  RegFileReadAAddress  : out    ProcessorRegisters;
			  RegFileReadBAddress  : out    ProcessorRegisters;
			  RegFileReadAEnable   : out    STD_LOGIC;
			  RegFileReadBEnable   : out    STD_LOGIC;
			  WriteRegistersFile   : out    STD_LOGIC;
			  RunningStatus        : out    STD_LOGIC;
           OutputEnable         : out    STD_LOGIC
			  );
  end component;
  
  component Datapath is
    Port ( InImediate          : in    STD_LOGIC_VECTOR ((bus_size - 6) downto 0);
	        InMemory            : in    STD_LOGIC_VECTOR ((bus_size - 1) downto 0);
           InExternal          : in    STD_LOGIC_VECTOR ((bus_size - 1) downto 0);
			  OutExternal         : inout STD_LOGIC_VECTOR ((bus_size - 1) downto 0);
			  Flags               : out   STD_LOGIC_VECTOR (3 downto 0);
			  SelMuxInput         : in    MultiplexSignals;
           SelAluOp            : in    ALU_operations;
			  SelShifterOp        : in    Shifter_operations;
			  RegFileWriteAddress : in    ProcessorRegisters;
			  RegFileReadAAddress : in    ProcessorRegisters;
			  RegFileReadBAddress : in    ProcessorRegisters;
			  RegFileReadAEnable  : in    STD_LOGIC;
			  RegFileReadBEnable  : in    STD_LOGIC;
			  WriteRegistersFile  : in    STD_LOGIC;
			  RegisterAValue      : out   STD_LOGIC_VECTOR ((bus_size - 1) downto 0);
			  RegisterBValue      : out   STD_LOGIC_VECTOR ((bus_size - 1) downto 0);
           OutputEnable        : in    STD_LOGIC
			  );
  end component;
  signal InImediate          : STD_LOGIC_VECTOR ((bus_size - 6) downto 0);
  signal InExternal          : STD_LOGIC_VECTOR ((bus_size - 1) downto 0);
  signal OutExternal         : STD_LOGIC_VECTOR ((bus_size - 1) downto 0);
  signal RegisterAValue      : STD_LOGIC_VECTOR ((bus_size - 1) downto 0);
  signal RegisterBValue      : STD_LOGIC_VECTOR ((bus_size - 1) downto 0);
  signal Flags               : STD_LOGIC_VECTOR (3 downto 0);  
  signal SelMuxInput         : MultiplexSignals;
  signal SelAluOp            : ALU_operations;
  signal SelShifterOp        : Shifter_operations;
  signal RegFileWriteAddress : ProcessorRegisters;
  signal RegFileReadAAddress : ProcessorRegisters;
  signal RegFileReadBAddress : ProcessorRegisters;
  signal RegFileReadAEnable  : STD_LOGIC;
  signal RegFileReadBEnable  : STD_LOGIC;
  signal WriteRegistersFile  : STD_LOGIC;
  signal OutputEnable        : STD_LOGIC;    
begin
  CrtlUn : ControlUnit port map(MEM_Data,MEM_Data_out,MEM_ReadAdd,MEM_WriteAdd,MEM_Read,MEM_Write,CLK,RESET,InImediate,Flags,RegisterAValue,RegisterBValue,SelMuxInput,SelAluOp,SelShifterOp,RegFileWriteAddress,RegFileReadAAddress,RegFileReadBAddress,RegFileReadAEnable,RegFileReadBEnable,WriteRegistersFile,RUN,OutputEnable);
  Dp : Datapath port map(InImediate,MEM_Data,External,External,Flags,SelMuxInput,SelAluOp,SelShifterOp,RegFileWriteAddress,RegFileReadAAddress,RegFileReadBAddress,RegFileReadAEnable,RegFileReadBEnable,WriteRegistersFile,RegisterAValue,RegisterBValue,OutputEnable);

end Behavioral;

